The present invention relates to a semiconductor memory device; and, more particularly, to a delay locked loop using a bi-directional ring oscillator and a counter unit.
In general, a delay locked loop (DLL) circuit reduces or compensates a skew between a clock signal and data or between an external clock and an internal clock, which is used in synchronizing an internal clock of a synchronous memory to an external clock without incurring any error. Typically, a timing delay occurs when a clock provided externally is used within the apparatus. The delay locked loop controls the timing delay to synchronize the internal clock to the external clock.
The synchronization between the internal and external clocks requires operations of compensating a jitter of the external clock with an internal delay locked loop, controlling a time delay unit such that a delay of the internal clock is less sensitive to noise introduced by a power supply or random noises, and fastening a locking time at maximum through the control of the time delay unit. A delay locked loop with a reduced jitter and an easily controllable time delay unit to satisfy the foregoing requirements has been recently presented in ISSCC paper in 1999, entitled xe2x80x9cA 250 Mb/s/pin 1 Gb Double Data Rate SDRAM with a Bi-Directional Delay and an Inter-Bank Shared Redundancy Schemexe2x80x9d by NEC Corporation.
FIG. 1 is a connection diagram of a conventional linear bi-directional delay DLL proposed by NEC Corporation.
Referring to FIG. 1, the conventional DLL includes an input unit 100, a first to a third D-flip flop 101, 103 and 104, a first inverter 102, a dummy delay unit 105, a first and a second AND gate 106 and 107, a first and a second bi-directional delay block 108 and 109, a first and a second pulse generation unit 110 and 111, and an OR gate 112.
The input unit 100 receives a clock signal CLK and a non-clock signal CLKB via positive and negative terminals respectively and compares received signals to produce a rising clock Rclk. The first D-flip slop 101 receives the rising clock Rclk as a clock signal and outputs a control signal with a pulse duration corresponding to one cycle of the rising clock Rclk. The first inverter 102 inverts the output of the first D-flip flop 101 to produce an inverted signal to be fed back as input to the first D-flip flop 101. The second D-flip flop 103 receives the output of the first D-flip flop 101 and the rising clock Rclk from the input unit 100 and produces a first forward signal FWD_A having a pulse duration corresponding to one cycle of the output of the first D-flip flop 101 and a first backward signal BWD_A having an opposite phase to the first forward signal FWD_A. The third D-flip flop 104 receives an inverted value of the output of the first D-flip flop 101 and the rising clock Rclk, and produces a second forward signal FWD_B having a pulse duration corresponding to one cycle of the output of the first D-flip flop 101 and a second backward signal BWD_B having an opposite phase to the second forward signal FWD_B.
The dummy delay unit 105 delays the rising clock Rclk by a skew to compensate the clock signal CLK. The first AND gate 106 logically combines the outputs of the second D-flip flop 103 and the dummy delay unit 105 to produce a combined output. The second AND gate 107 logically combines the outputs of the third D-flip flop 104 and the dummy delay unit 105 to produce a combined output.
The first bi-directional delay block 108 including a multiplicity of unit bi-directional delays which are connected serially, receives the output of the first AND gate 106 and controls a time delay in a first or second direction under the control of the first forward signal FWD_A and the first backward signal BWD_A.
The second bi-directional delay block 109 including a multiplicity of unit bi-directional delays which are connected in series, receives the output of the second AND gate 107 and controls a time delay in the first or second direction under the control of the second forward signal FWD_B and the second backward signal BWD_B.
The first pulse generation unit 110 generates a pulse at a rising and a falling edge of the output of the first bi-directional delay block 108. The second pulse generation unit 111 generates a pulse at a rising and a falling edge of the output of the second bi-directional delay block 109. The OR gate 112 performs an OR operation on the outputs of the first and second pulse generation units 110 and 111.
FIG. 2A is a connection diagram of a conventional unit bi-directional delay, which has been proposed by FUJITSU Ltd.
As shown in FIG. 2A, the unit bi-directional delay proposed by FUJITSU includes four three-phase buffers 200, 201, 202 and 203.
The first three-phase buffer 200 receives one of the outputs of the first and second AND gates as a first input signal Am to produce a second control signal Bm, wherein the gate of a PMOS transistor is controlled by the first or second backward signal (hereinafter called BWD) and the gate of an NMOS transistor is controlled by the first or second forward signal (hereinafter called FWD). The second three-phase buffer 201 receives the second output signal Bm, wherein the gate of a PMOS transistor is controlled by the BWD signal and the gate of an NMOS transistor is controlled by the FWD signal.
The third three-phase buffer 202 receives the output of a unit bi-directional delay at a previous stage as a second input signal Bm+1, to produce a first output signal Am+1, wherein the gate of a PMOS transistor is controlled by the backward signal BWD and the gate of an NMOS transistor is controlled by the forward signal FWD.
The fourth three-phase buffer 203 receives the first output signal Am+1 to produce the second output signal Bm, wherein the gate of a PMOS transistor is controlled by the forward signal FWD and the gate of an NMOS transistor is controlled by the backward signal BWD.
When the forward signal FWD is logic high and the backward signal BWD is logic low, the first and second three-phase buffers 200 and 201 are activated to provide input signal to the first direction (i.e., the forward direction). When the forward signal FWD is logic low and the backward signal BWD is logic high, the third and fourth three-phase buffers 202 and 203 are activated to provide input signal to the second direction (i.e., the backward direction).
FIG. 2B is a symbolic diagram of the unit bi-directional delay shown in FIG. 2A. The construction and operation of the device in FIG. 2B is similar that of the device previously described in conjunction with FIG. 2A and therefore a further description thereof is omitted.
FIG. 2C is a connection diagram of the unit bi-directional delay proposed by NEC Corporation.
As shown in FIG. 2C, a difference between NEC and FUJITSU is that the PMOS transistor is removed in the first and fourth three-phase buffers 200 and 203, and the NMOS transistor is removed in the second and third three-phase buffers 201 and 202, preventing both of the first and second input signals Am and Bm+1 with a logic low value from being transmitted to corresponding buffers.
Although the construction of the delay locked loop described above generates a DLL signal at the rising clock Rclk of the clock signal CLK, the construction for the rising clock Rclk is similar to that of a delay locked loop for outputting the DLL signal at the falling clock Fclk of the clock signal CLK except that the output signal of the input unit 100 is a falling clock.
FIG. 3 is a timing diagram illustrating the operating principle of the first and second bi-directional delay blocks.
Referring to FIG. 3, in case the first forward signal FWD_A is logic high and the first backward signal BWD_A is logic low, when the first output signal A0_A is rendered to a logic high after a compensation skew tdm, the logic high signal A0_A is propagated to the first direction (i.e., the forward direction). In this case, there is a prior condition that all the forward nodes (Am_A, m=0, 1, 2, . . . , 40) should be set to logic low and all the backward nodes (Bm_B, m=0, 1, 2, . . . , 40) should be set to logic high. Since rendering of the forward node to logic high allows the backward node corresponding thereto to be rendered to logic low, it is necessary to set the backward node to logic low in all positions to which the logic high is transmitted.
Thereafter, the first forward signal FWD_A is rendered to a logic low and the first backward signal BWD_A is rendered to a logic high, at the same time that the logic high signal is propagated to the second direction (i.e., the backward direction) to thereby render the first output signal B0xe2x80x94A to a logic high after an interval tclk-tdm, wherein tclk is one clock cycle. That is, the signal precedes a rising edge of a subsequent clock by tdm. As mentioned above, since a signal preceding the rising edge by tdm per two clock cycles may be obtained, an additional bi-directional delay line is provided, and the delay lines are operated alternatively, allowing as DLL clock to be obtained at each cycle. The logic high of the second output signal B0_A means that all the backward nodes have been rendered to logic high and also all the forward nodes have been rendered to logic low. In short, a reset may be automatically performed for subsequent processes without any reset operation.
The delay locked loop may be implemented with the bi-directional delay. However, in low frequency applications, the interval tclk-tdm increases with an increase in one clock cycle tclk, so that the bi-directional delay line should be lengthened by an increased interval. That is, many unit bi-directional delays are additionally required.
The first and second bi-directional delay blocks 108 and 109 of the delay locked loop shown in FIG. 1 include 40 stages of unit bi-directional delays to adjust a time delay in low frequency applications, and four control signal lines to be used in controlling each of the unit bi-directional delays.
Accordingly, the prior art imposes great chip area requirements, which, in turn, may decrease the number of chips per wafer, thereby leading to increase in cost for the apparatus.
It is, therefore, a primary object of the present invention to provide a delay locked loop, which is capable of achieving a reduced jitter and a stable time delay adjustment, to thereby perform a bi-directional time delay with a small area even in low frequency applications.
In accordance with a preferred embodiment of the present invention, there is provided a delay locked loop for use in a semiconductor memory device, which comprises: an input unit for receiving a clock signal and a non-clock signal and comparing received signals to produce an internal clock signal; a controller for receiving the internal clock to produce a first forward signal and a second backward signal each having a pulse duration corresponding to one cycle of the clock signal, a first backward signal and a second forward signal each having an opposite phase to the first forward signal and the second backward signal, and a first and a second start signal each having a pulse duration corresponding to a time delay to be compensated; a bi-directional oscillator, responsive to the second forward signal, the second backward signal and the second start signal, for performing a ring oscillation in a first or second direction and fulfilling an addition and subtraction adjustment function for a time delay; a counter for receiving an output signal of the bi-directional oscillator and counting the ring oscillations; and an output means for performing a combination operation on the outputs of the bi-directional oscillator and the counter, to produce the result as a final internal clock signal.
By changing a linear structure into a ring structure, the present invention employs only four stages of unit bi-directional delay block and a three-bits counter to allow an operation to be performed at frequencies up to 40 MHz. Also, the present invention employs only four stages of unit bi-directional delay block and a four-bits counter to allow the operation to be performed at frequencies up to 20 MHz. Accordingly, the present invention has the ability to implement a delay locked loop with a reduced layout requirement even at a low frequency of 25 MHz corresponding to a wafer test frequency.
The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which:
FIG. 1 shows a connection diagram of a conventional linear bi-directional delay DLL proposed by NEC Corporation;
FIG. 2A is connection diagram of a conventional unit bi-directional delay which has been proposed by FUJITSU Ltd.;
FIG. 2B is a symbolic diagram of the unit bi-directional delay shown in FIG. 2A;
FIG. 2C is a connection diagram of the unit bi-directional delay proposed by NEC Corporation;
FIG. 3 is a timing diagram illustrating the operating principle of the first and second bi-directional delay blocks;
FIG. 4 is a connection diagram of a delay locked loop in accordance with preferred embodiments of the present invention;
FIG. 5 is a timing diagram illustrating a flow of control signals output from the controller 410 of the present invention;
FIG. 6A is a block diagram showing that a unit bi-directional inverter is inserted at the linear bi-directional delays;
FIG. 6B is a schematic block diagram illustrating the principle of the bi-directional ring oscillator 421 in accordance with a preferred embodiment of the present invention;
FIG. 7A is a connection diagram of the unit bi-directional delay 426 in a first stage in accordance with the present invention;
FIG. 7B is a symbolic diagram of the unit bi-directional delay shown in FIG. 7A in accordance with the present invention;
FIG. 8A is a connection diagram of the unit bi-directional inverter 429 of present invention;
FIG. 8B is a connection diagram in which three unit bi-directional inverters are connected in series for simulation; and
FIG. 9 is a timing diagram of signal waveforms in accordance with the present invention.